Caltech Mixed-Signal, RF & Microwave Seminar

Despite the ever-increasing desire to build custom SoCs with substantial analog or mixed-signal content in order to most efficiently serve today's power- and battery-limited applications, analog IC design has remained a nearly entirely manual endeavor, and is often a key bottleneck in overall time-to-market.  This talk will therefore start by describing my group's recent efforts to develop an approach that begins to address this issue by enabling designers to capture and codify the methodologies they themselves use to design analog circuits in to executable generators.  By shifting the goal of a designer to writing such a generator – as opposed to producing a specific instance of a particular circuit – productivity can be substantially enhanced since a change in specifications and/or process technology simply requires re-running the generator.  The framework we have developed  to enable this is called the Berkeley Analog Generator (BAG), and during this talk I will describe some of its key features – most importantly, the approach we have taken to enable such generators to produce carefully controlled and crafted layouts.  My group has used BAG to develop a number of test-chips over the past few years – including a 60Gb/s wireline receiver front-end realized in a 65nm CMOS process and dissipating <3pJ/bit.  Thus, in the second half of the talk I will not only describe the circuit and equalization architecture that enabled these results, but also highlight how BAG was applied to produce the high-speed core of the receiver.