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Caltech

EE Seminar

Friday, March 24, 2017
4:00pm to 5:00pm
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Moore B280
Engineering 2D Materials for Nanoelectronic Devices in the Ultraclean Limit
Lei Wang, Cornell University,

As the conventional silicon electronic devices reach the dimensional scaling limit for better performance, other candidates like spintronics, quantum computing, tunneling transistors and valleytronics on new material systems are intensively being explored for possible future electronics. Two-dimensional (2D) material is one of the important platforms for these novel systems. Although 2D materials such as graphene are promised to carry remarkable electronic performance, the experimental reality is that they are highly sensitive to disorder from the environment. I will present the techniques I developed to controllably 'sandwich' graphene between insulating hexagonal boron nitride crystals, which dramatically reduces disorder and approaches the ideal behavior in the electron transport on graphene [1]. I will also discuss about how to achieve the lowest electrical contact resistance to the fully encapsulated graphene layer through its 1D edge only [1]. In addition, these new techniques allow us to stack different 2D materials together layer by layer to form heterostructures, with controlling their positions, thickness and lattice mismatch angles. I will talk about how to tune these nobs to achieve the bandstructure engineering [2] at the interfaces between the different atomic planes and the new physics [3] revealed by these structures. I will conclude my talk by presenting a few future directions addressing the scalability and possible applications in optoelectronics, valleytronics and energy harvesting [4].

 

[1] L. Wang et al, Science, 614-617 (2013).

[2] C. Dean, L. Wang et al, Nature 497, 598-602 (2013).

[3] L. Wang et al, Science 350, 1231-1234 (2015).

[4] W. Wu, L. Wang et al, Nature 514, 470-474 (2014).