High Energy Physics Seminar

With the HL-LHC ahead, bringing the discrimination power of offline reconstruction algorithms to Level 1 trigger selection will be a major asset to guarantee an optimal usage of the limited trigger resources at downstream steps. To do so, the CMS experiment is intensively investigating the possibility of running the particle-flow reconstruction algorithm on low-latency FPGA cards, part of the L1 hardware electronics, taking advantage of the advent of track reconstruction at L1. This technological revolution will make it possible to use advanced pileup mitigations techniques, such as pileup per particle identification (PUPPI), already in the L1 reconstruction, reconceptualising algorithms for L1 trigger at hadron colliders and with great advantage for HLT and offline selections downstream, and eventually for physics analysis.

The talk will present proof-of-principle studies on both physics and hardware performance of prototype jet algorithms foreseen by CMS for the HL-LHC. Furthermore, the availability of particle candidates at L1 opens the possibility to use raw information as inputs to machine learning methods, which are becoming ubiquitous across particle physics. Tthe exploration of such techniques in low-latency environments like L1 trigger systems has only just begun. The talk will present new software, based on High Level Synthesis, to generically port several kinds of network models (BDTs, DNNs, CNNs) into FPGA firmware. A set of general practices to efficiently design low-latency machine-learning algorithms on FPGAs will be described.